Image Computing Hardware Architecture With High Power

Integral image computing is an important part of many vision applications and is characterized by intensive computation and frequent memory accessing. This brief proposes an approach for fast integral imagecomputing with high area and power efficiency. For the data flow of the integral image computation a dual-direction data-oriented integral imagecomputing mechanism is proposed to improve the processing efficiency, and then a pipelined parallel architecture is designed to support this mechanism.

The parallelism and time complexity of the approach are analyzed and the hardware implementation cost of the proposed architecture is also presented. Compared with the state-of-the-art methods this architecture achieves the highest processing speed with comparatively low logic resources and power consumption.