• Matlab
  • Simulink
  • NS3
  • OMNET++
  • NS2

ERSFQ 8 Bit Parallel Adders as a Process Benchmark

We have designed and demonstrated two versions of an ERSFQ 8-bit parallel adder. ERSFQ is a resistor-free approach to dc biasing of Single Flux Quantum circuits that dissipates orders of magnitude less power than a traditional RSFQ logic while operating and has zero dissipation in inactive mode.

The adders were designed for and fabricated with various fabrication processes, including HYPRES’s 1.0-μm 4-layer 4.5 kA/cm2 process, HYPRES’s 0.25-μm 4-layer 4.5 kA/cm2 process, HYPRES’s 0.25-μm 6-layer 4.5 kA/cm2 planarized process, and MIT Lincoln Lab’s 0.25-μm 4-layer 10 kA/cm2 process. These circuits serve as a good LSI fabrication process benchmark. We describe design and report on test results of all versions of the adder.

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