Gate Induced Leakage in Silicon Nanowire Transistors
In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies. The results show that the SNWTs will suffer from a more severe GIDL issue in small diameter (Dnw) devices under low IVgsI. It is believed that this unexpected GIDL problem in SNWTs origins from the longitudinal band-to-band tunneling (L-BTBT) at the body/drain junction enhanced by the strong gate coupling to the depletion region, which usually can be neglected in planar devices.
On the other hand, the traditional transverse BTBT (T-BTBT) only dominates at high IVgsI with relatively large Dnw. Systematic study of GIDL dependence on process parameters, including Dnw cross-sectional shape, doping, and overlap length (Lov), shows that both T-BTBT and L-BTBT can be alleviated by reducing the doping and rounding the corner, but L-BTBT is worsened by reducing Dnw and Lov despite of the alleviated T-BTBT. As the extension process engineering strongly impacts the short-channel effect and driving current of SNWTs, a GIDL optimization strategy considering the leakage power and device performance is given for low-power SNWT design.
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