Gate Induced Leakage in Silicon Nanowire Transistors

In this paper, detailed physical mechanisms of gate-induced drain leakage (GIDL) in gate-all-around silicon nanowire transistors (SNWTs) are investigated and verified by experiments and TCAD studies. The results show that the SNWTs will suffer from a more severe GIDL issue in small diameter (D_nw) devices under low IV_gsI. It is believed that this unexpected GIDL problem in SNWTs origins from the longitudinal band-to-band tunneling (L-BTBT) at the body/drain junction enhanced by the strong gate coupling to the depletion region, which usually can be neglected in planar devices.

On the other hand, the traditional transverse BTBT (T-BTBT) only dominates at high IV_gsI with relatively large D_nw. Systematic study of GIDL dependence on process parameters, including D_nw cross-sectional shape, doping, and overlap length (L_ov), shows that both T-BTBT and L-BTBT can be alleviated by reducing the doping and rounding the corner, but L-BTBT is worsened by reducing D_nw and L_ov despite of the alleviated T-BTBT. As the extension process engineering strongly impacts the short-channel effect and driving current of SNWTs, a GIDL optimization strategy considering the leakage power and device performance is given for low-power SNWT design.