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Sense amplifier based flip flop for low power systems
A novel low-power sense-amplifier-based flip-flop (FF) is presented. Using a simplified single-ended pass transistor-based latch design, the loading of the sense amplifier is greatly alleviated, which facilitates a size reduced sense-amplifier design as well.
These factors improve the power consumption and the delay of the FF design substantially and the performance claims are verified through extensive post-layout simulations.
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