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VLSI implementation of coupled MRF model

Efficient pixel-parallel image processing using a pulse-coupled phase oscillator model and its very large scale integration (VLSI) implementation is proposed. A processing unit that corresponds to a pixel of an image transmits spike pulses to other units, and updates its own analogue state value at timing when spikes come from other units. From a VLSI implementation point of view, this mechanism is suitable for very low-power operation because analogue buffers are unnecessary for data transmission.

On the basis of this model, a VLSI image processor chip that performs a coupled Markov random field model for image region segmentation is designed and fabricated. A very low-power VLSI design has been achieved by the combination of an analogue oscillator and digital coupling function generator circuits with time-domain computation. The processing performance of the fabricated oscillator-based image processor chip using a 0.25 μm CMOS process has achieved 43.2 GOPS or 656 GOPS/W. Experiments using the fabricated chip have shown successful image region segmentation in one- and two-dimensional images.

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