Electro Thermal Reliability Modelling of Bipolar Latch up
In this paper, a compact dynamic and fully-coupled electro-thermal model for parasitic BJT latch-up is presented and validated by measurements. The model can be used to enhance the reliability of the latest generation of commercially available power devices. BJT latch-up can be triggered by body-diode reverse-recovery, hard commutation with high dV/dt or from avalanche conduction during unclamped-inductive-switching. In the case of body-diode reverse-recovery, the base current that initiates BJT latch-up is calculated from the solution of the ambipolar diffusion equation describing the minority carrier distribution in the anti-parallel PiN body-diode.
For hard commutation with high dV/dt, the displacement current of the drain-body charging capacitance is critical for BJT latch-up whereas for avalanche conduction, the base current is calculated from impact ionization. The parasitic BJT is implemented in Simulink using the Ebers-Moll model and the temperature is calculated using a thermal network matched to the transient thermal impedance characteristic of the devices. This model has been applied to CoolMOS and SiC MOSFETs. Measurements show that the model correctly predicts BJT latch-up during reverse-recovery as a function of forward-current density and temperature. The model presented, when calibrated correctly by device manufacturers and applications engineers, is capable of bench-marking the robustness of power-MOSFETs
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